Impact of Sharing-Based Thread Placement on Multithreaded Architectures

Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interference and degrade overall performance. One technique to reduce the interconnect traffic is to co-locate threads that share data on the same processor. Multiple threads sharing in the cache should reduce compulsory and invalidation misses, thereby improving execution time. To test this hypothesis, we compared a variety of thread placement algorithms via trace-driven simulation of fourteen coarse- and medium-grain parallel applications on several multithreaded architectures. Our results contradict the hypothesis. Rather than decreasing, compulsory and invalidation misses remained nearly constant across all placement algorithms, for all processor configurations, even with an infinite cache. That is, sharing-based placement had no (positive) effect on execution time. Instead, load balancing was the critical factor ...

• Type: Conference
• Year: 1994
• Where: ISCA
• Authors: Radhika Thekkath, Susan J. Eggers
• Keywords: Hardware, Invalidation Misses, ISCA 1994, Multithreaded Architectures, Placement Algorithms