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EUROPAR
2003
Springer

Implementation and Performance Evaluation of M-VIA on AceNIC Gigabit Ethernet Card

10 years 4 months ago
Implementation and Performance Evaluation of M-VIA on AceNIC Gigabit Ethernet Card
This paper describes the implementation and performance of M-VIA on the AceNIC Gigabit Ethernet card. The AceNIC adapter has several notable hardware features for high-speed communication, such as jumbo frames and interrupt coalescing. The M-VIA performance characteristics were measured and evaluated based on these hardware features. Our results show that latency and bandwidth improvement can be obtained when the M-VIA data segmentation size is properly adjusted to utilize the AceNIC’s jumbo frame feature. The M-VIA data segmentation size of 4,096 bytes with MTU size of 4,138 bytes showed the best performance. However, larger MTU sizes did not necessarily result in better performance due to extra segmentation and DMA setup overhead. In addition, the cost of M-VIA interrupt handling can be reduced with AceNIC’s hardware interrupt coalescing. When the parameters for the hardware interrupt coalescing were properly adjusted, the latency of interrupt handling was reduced by up to 170 µ...
In-Su Yoon, Sang-Hwa Chung, Ben Lee, Hyuk-Chul Kwo
Added 06 Jul 2010
Updated 06 Jul 2010
Type Conference
Year 2003
Where EUROPAR
Authors In-Su Yoon, Sang-Hwa Chung, Ben Lee, Hyuk-Chul Kwon
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