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ASPDAC
2011
ACM

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

8 years 10 months ago
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous FPGA, the power consumption is reduced by 38% for the workload of 15%.
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama
Added 24 Aug 2011
Updated 24 Aug 2011
Type Journal
Year 2011
Where ASPDAC
Authors Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
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