Improving the Average Delay of Sorting

In previous work we have introduced an average-case measure for the time complexity of Boolean circuits – that is the delay between feeding the input bits into a circuit and the moment when the results are ready at the output gates – and analysed this complexity measure for prefix computations. Here we consider the problem to sort large integers that are given in binary notation. Contrary to a word comparator sorting circuit C where a basic computational element, a comparator, is charged with a single time step to compare two elements, in a bit comparator circuit C a comparison of two binary numbers has to be implemented by a Boolean subcircuit CM called comparator module that is built from Boolean gates of bounded fanin. Thus, compared to C, the depth of C will be larger by a factor up to the depth of CM. Our goal is to minimize the average delay of bit comparator sorting circuits. The worst-case delay can be estimated by the depth of the circuit. For this worst-case measure two ...

• Type: Conference
• Year: 2007
• Where: TAMC
• Authors: Andreas Jakoby, Maciej Liskiewicz, Rüdiger Reischuk, Christian Schindelhauer
• Keywords: Bit Comparator, Comparator, Comparator Sorting Circuits, TAMC 2007