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MICRO
1995
IEEE

Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation

12 years 3 months ago
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be applied to increase instruction-level parallelism. Thispaper describes and evaluatesa software technique, dynamic memory disambiguation, thatpermits loops containing loads and stores to be scheduled more aggressively, thereby exposing more instruction-level parallelism. The results of our evaluation show that when dynamic memorydisambiguationis applied in conjunction with loop unrolling, register renaming,and static memory disambiguation, the ILP of memory-intensivebenchmarks can be increased by as much as 300 percent over loops where dynamic memory disambiguation is not performed. Our measurementsalso indicate thatfor theprograms that benefit the most from these optimizations, the register usage does not exceed the number of registers on most high-performunceprocessors.
Jack W. Davidson, Sanjay Jinturkar
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where MICRO
Authors Jack W. Davidson, Sanjay Jinturkar
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