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Improving Memory Latency Aware Fetch Policies for SMT Processors

10 years 5 months ago
Improving Memory Latency Aware Fetch Policies for SMT Processors
Abstract. In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determining how shared resources are allocated. When a thread experiences an L2 miss, critical resources can be monopolized for a long time choking the execution of the remaining threads. A primary task of the instruction fetch policy is to prevent this situation. In this paper we propose novel improved versions of the three best published policies addressing this problem. Our policies significantly enhance the original ones in throughput, and fairness, also reducing the energy consumption.
Francisco J. Cazorla, Enrique Fernández, Al
Added 07 Jul 2010
Updated 07 Jul 2010
Type Conference
Year 2003
Where ISHPC
Authors Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero
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