Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture

The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changes to the core design and could thus be easily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Appl...

• Type: Conference
• Year: 2009
• Where: ARCS
• Authors: Joseph Gebis, Leonid Oliker, John Shalf, Samuel Williams, Katherine A. Yelick
• Keywords: ARCS 2009, Scratchpad, Software Controlled Scratchpad, Software-controlled Scratchpad Memory, System Software