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HIPEAC
2010
Springer

Improving Performance by Reducing Aborts in Hardware Transactional Memory

10 years 3 months ago
Improving Performance by Reducing Aborts in Hardware Transactional Memory
The optimistic nature of Transactional Memory (TM) systems can lead to the concurrent execution of transactions that are later found to conflict. Conflicts degrade scalability, and may lead to aborts that increase wasted work, and degrade performance. A promising approach to reducing conflicts at runtime is dynamically, and transparently, reordering the execution of transactions upon discovery of conflicts. This approach has been explored in Software TMs (STMs), but not in Hardware TMs (HTMs). Furthermore, STM implementations of this approach cannot be ported to HTMs easily. This paper investigates the feasibility of such reordering in HTMs, and presents two designs that are scalable, independent of the on-chip interconnect, require only minor modifications to each core, and add no execution overhead if no conflicts occur. The evaluation takes LogTM-SE as a base line and considers benchmarks with different levels of contention (transactional conflicts). The results show that the...
Mohammad Ansari, Behram Khan, Mikel Luján,
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2010
Where HIPEAC
Authors Mohammad Ansari, Behram Khan, Mikel Luján, Christos Kotselidis, Chris C. Kirkham, Ian Watson
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