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FPL
2007
Springer

Improving Pipelined Soft Processors with Multithreading

13 years 9 months ago
Improving Pipelined Soft Processors with Multithreading
Designers of FPGA-based systems are increasingly including soft processors—processors implemented in programmable logic—in their designs. Any combination of area, clock frequency, performance, and power may be of importance in the choice of a soft processor design to use, motivating area efficiency as the best metric with which to compare potential designs. In this paper we demonstrate that 3, 5, and 7-stage pipelined multithreaded soft processors are 33%, 77%, and 106% more area efficient than their singlethreaded counterparts, the result of careful tuning of the architecture, ISA, and number of threads.
Martin Labrecque, J. Gregory Steffan
Added 07 Jun 2010
Updated 07 Jun 2010
Type Conference
Year 2007
Where FPL
Authors Martin Labrecque, J. Gregory Steffan
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