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2006
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Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)

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Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two circuit-level techniques to efficiently yet economically improve SEU tolerance of static CMOS digital circuits. We also developed a “RObustness COmpiler (ROCO)” to integrate these techniques into the existing design flow to achieve high level of reliability at low design cost. Experiment results show that the proposed methodology is able to greatly improve the circuits’ SEU tolerance with zero timing overhead and very limited area penalty.
Chong Zhao, Sujit Dey
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where ISQED
Authors Chong Zhao, Sujit Dey
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