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DATE
2005
IEEE

An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

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An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to FieldProgrammable Gate Array (FPGA) platforms is concerned.
Rui Rodrigues, João M. P. Cardoso
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where DATE
Authors Rui Rodrigues, João M. P. Cardoso
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