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MICRO
1996
IEEE

Instruction Scheduling and Executable Editing

9 years 6 months ago
Instruction Scheduling and Executable Editing
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and actual performance, while frustrating for computer architects and chip manufacturers, opens the exciting possibility of low-cost instrumentation for measurement, simulation, or emulation. Instrumentation code that executes in previously unused processor cycles is effectively hidden. On two superscalar SPARC processors, a simple, local scheduler hid an average of 13% of the overhead cost of profiling instrumentation in the SPECINT benchmarks and an average of 33% of the profiling cost in the SPECFP benchmarks.
Eric Schnarr, James R. Larus
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1996
Where MICRO
Authors Eric Schnarr, James R. Larus
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