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ASPDAC
2004
ACM

Instruction set and functional unit synthesis for SIMD processor cores

11 years 5 months ago
Instruction set and functional unit synthesis for SIMD processor cores
—This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given timing constraint. The promising experimental results are also shown.
Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka,
Added 30 Jun 2010
Updated 30 Jun 2010
Type Conference
Year 2004
Where ASPDAC
Authors Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
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