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ISCAS
2008
IEEE

Integrated circuit implementation of a cortical neuron

9 years 8 months ago
Integrated circuit implementation of a cortical neuron
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The single neuron cell has a compact layout and very low energy consumption, in the range of 9 pJ per spike. Experimental results demonstrate the capability of the circuit to generate a realistic spike shape and a variety of spiking and bursting firing patterns. The models of various cortical neuron types are obtained in a single circuit, through the adjustment of two biasing voltages, making the circuit suitable for applications in reconfigurable neuromorphic devices that implement biologically plausible spiking neural networks.
Jayawan H. B. Wijekoon, Piotr Dudek
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where ISCAS
Authors Jayawan H. B. Wijekoon, Piotr Dudek
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