Sciweavers

Share
LCTRTS
2007
Springer

Integrated CPU and l2 cache voltage scaling using machine learning

9 years 4 months ago
Integrated CPU and l2 cache voltage scaling using machine learning
Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applications. Unfortunately, adding more resources typically comes on the expense of higher energy costs. New chip designwith Multiple Clock Domains (MCD) opens the opportunity for fine-grain power management within the processorchip. When used with dynamic voltage scaling (DVS), we can control the voltage and power of each domain independently. A significant power and energy improvement has been shown when using MCD design in comparison to managing a single voltage domain for the whole chip, as in traditional chips with global DVS. In this paper, we propose PACSL a Power-Aware Compilerbased approach using Supervised Learning. PACSL automatically derives an integrated CPU-core and on-chip L2 cache DVS policy tailored to a specific system and workload. Our approach uses supervised machine learning to discover a poli...
Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Ru
Added 08 Jun 2010
Updated 08 Jun 2010
Type Conference
Year 2007
Where LCTRTS
Authors Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Rusu, Ruibin Xu, Frank Liberato, Bruce R. Childers, Daniel Mossé, Rami G. Melhem
Comments (0)
books