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SLIP
2009
ACM

Integrated interlayer via planning and pin assignment for 3D ICs

9 years 6 months ago
Integrated interlayer via planning and pin assignment for 3D ICs
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the key challenges is the vertical interlayer via used for different device layers connection. In this paper, we use min-cost maximum flow algorithm for integrated interlayer via planning and pin assignment for all two-pin nets from one source block to all the other blocks, which make sure interlayer via is inserted as successfully as possible with the shortest wire length. By iteratively using this algorithm with other auxiliary methods on each block, we can deal with the problem for all nets among blocks in 3D ICs. Experimental results show its efficiency and effectiveness. To our knowledge, this is the first algorithm of interlayer via planning with pin assignment for 3D ICs. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids – Placement and routing. General Terms Algorithms, Design...
Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto
Added 28 May 2010
Updated 28 May 2010
Type Conference
Year 2009
Where SLIP
Authors Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto
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