An integrated nonlinear placement framework with congestion and porosity aware buffer planning

Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number of buffers may cause not only dramatic cell migration but also routing hotspots. If buffering is not controlled well, it may fail to close a design. Placement with buffer porosity awareness can allocate space for inserting these buffers, and buffering with congestion awareness can increase the routability. Therefore, there is essential need for a placement framework with porosity and routing congestion aware buffer planning. We propose the first integrated nonlinear placement framework with porosity and congestion aware buffer planning. We demonstrate the integration of increasingly refined routing congestion aware buffer planning and insertion methodology in a high quality nonlinear placer. Our experiments show the improvement of average routing overflow by 69%, average wirelength by 28% and average buffer ...

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan
• Keywords: Aware Buffer Planning, Buffer Porosity Awareness, Congestion Aware Buffer, DAC 2008, Design Automation