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2006
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Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization

9 years 7 months ago
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly complex task due to its enormous solution space. This paper presents the first algorithm that performs retiming and simultaneous supply/threshold voltage scaling. In our three-step approach, low power retiming is first performed to reduce the clock period while taking the FF delay/power into consideration. Next, the subsequent voltage scaling makes the best possible supply/threshold voltage assignment under the given clock period constraint set by the retiming. Finally, a post-process further refines the voltage scaling solution by exploiting the remaining timing slack in the circuit. Related experiments show that our min-FF retiming plus simultaneous Vdd/Vth scaling approach reduces the total power consumption by 34% on average compared to the existing max-FF retiming plus Vdd Scaling approach. Categories...
Mongkol Ekpanyapong, Sung Kyu Lim
Added 14 Jun 2010
Updated 14 Jun 2010
Type Conference
Year 2006
Where ISPD
Authors Mongkol Ekpanyapong, Sung Kyu Lim
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