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DAC
1996
ACM

Integrating Formal Verification Methods with A Conventional Project Design Flow

9 years 9 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional project design flow. The methodology has been used successfully to verify the protocols within a distributed shared memory machine. We consider the following to be the four main benefits to using the model checker. First, it ensures that there exists an accurate high-level machine readable system specification. Second, it allows high-level system verification early in the design phase. Third, it facilitates equivalence and refinement checking between the high-level specification, and the RTL implementation. Finally, and most importantly it uncovered many protocol specification and RTL implementation problems.
Ásgeir Th. Eiríksson
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1996
Where DAC
Authors Ásgeir Th. Eiríksson
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