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2005
IEEE

Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems

10 years 5 months ago
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other planes which provide analog processing, digital signal processing, and wireless communication/networking. The sensor plane contains four types of transducers: visible imager (Active Pixel Sensor), near IR and mid IR imager, and seismic and acoustic sensor arrays. This paper investigates ways of introducing defect and fault tolerance into the inter-plane via connections between the sensor and digital signal processing planes. The methodology detects failures in the inter-plane vias by inputting controlled signal patterns in each sensor type on the sensor plane. The sensor/via fault distribution in turn impacts the defect avoidance in the fault tolerant TESH network, which binds both the sensors and the processors that analyze and fuse the sensor plane data. Fault tolerance in the design and fabrication of the...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where DFT
Authors Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
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