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ICCAD
1997
IEEE

Interconnect design for deep submicron ICs

10 years 5 months ago
Interconnect design for deep submicron ICs
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we present commonly used interconnect models and a set of interconnect design and optimization techniques for improving interconnect performance and reliability. Finally, we present comparisons of different optimization techniques in terms of their efficiency and optimization results, and show the impact of these optimization techniques on interconnect performance in each technology generation from the 0.35¢¤£ to 0.07¢¤£ projected in the National Technology Roadmap for Semiconductors. I. INTERCONNECT TRENDS AND CHALLENGES The driving force behind the impressive advancement of the VLSI circuit technology has been the rapid scaling of the feature size, i.e., the minimum dimension of the...
Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok K
Added 06 Aug 2010
Updated 06 Aug 2010
Type Conference
Year 1997
Where ICCAD
Authors Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo
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