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LCTRTS
2007
Springer

Interface synthesis for heterogeneous multi-core systems from transaction level models

9 years 4 months ago
Interface synthesis for heterogeneous multi-core systems from transaction level models
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters in the platform and generates interface modules called universal bridges between buses in the design. The design and configuration of the bridges depend on several platform components including heterogeneity of the components, traffic on the bus, size of messages and so on. We define these parameters and show how the synthesizable RTL code for the bridge can be automatically derived based on these parameters. We use industrial strength design drivers such as an MP3 decoder to test our automatically generated bridges for a variety of platforms and compare them to manually designed bridges on different quality metrics. Our experimental results show that performance of automatically generated bridges are within 5% of manual design for simple platforms but surpasses them for more complex platforms. The area and...
Hansu Cho, Samar Abdi, Daniel Gajski
Added 08 Jun 2010
Updated 08 Jun 2010
Type Conference
Year 2007
Where LCTRTS
Authors Hansu Cho, Samar Abdi, Daniel Gajski
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