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DATE
2006
IEEE

An interprocedural code optimization technique for network processors using hardware multi-threading support

9 years 8 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level code compilation always introduces overhead, regarding code size and performance compared to handwritten assembly code. This overhead results partially from high-level function calls that usually introduce memory accesses in order to save and reload register contents. A key feature of many NPU architectures is hardware multithreading support, in the form of separate register files, for fast context switching between different application tasks. In this paper, a new NPU code optimization technique to use such HW contexts is presented that minimizes the overhead for saving and reloading register contents for function calls via the runtime stack. The feasibility and the performance gain of this technique are demonstrated for the Infineon Technologies PP32 NPU architecture and typical network application kernel...
Hanno Scharwächter, Manuel Hohenauer, Rainer
Added 10 Jun 2010
Updated 10 Jun 2010
Type Conference
Year 2006
Where DATE
Authors Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
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