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DAC
2002
ACM

IP delivery for FPGAs using Applets and JHDL

9 years 10 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of applicationspecific circuits. Applets can be customized to provide varying levels of IP visibility and functionality as needed by both customer and vendor. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids--Simulation, Hardware description languages General Terms Design Keywords Intellectual Property, JHDL, Applet, FPGA
Michael J. Wirthlin, Brian McMurtrey
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2002
Where DAC
Authors Michael J. Wirthlin, Brian McMurtrey
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