IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter

In this paper we describe a parameterizable FPGA-based implementation of a sigma-delta converter used in a 96kHz audio DAC. From specifications of the converter’s input bitwidth and data sampling frequency, VHDL generic parameters are used to automatically generate the required design. The resulting implementation is optimized to use the minimum internal wordlength and number of stages. We prototyped the converter on an FPGA board for verification purposes and the results are presented.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
• Keywords: Converter’s Input Bitwidth, FPL 2004, Parameterizable Fpga-based Implementation, VHDL Generic Parameters