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2007
Springer

Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations

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Iteration Bound Analysis and Throughput Optimum Architecture of SHA-256 (384, 512) for Hardware Implementations
Abstract. The hash algorithm forms the basis of many popular cryptographic protocols and it is therefore important to find throughput optimal implementations. Though there have been numerous published papers proposing high throughput architectures, none of them have claimed to be optimal. In this paper, we perform iteration bound analysis on the SHA2 family of hash algorithms. Using this technique, we are able to both calculate the theoretical maximum throughput and determine the architecture that achieves this throughput. In addition to providing the throughput optimal architecture for SHA2, the techniques presented can also be used to analyze and design optimal architectures for some other iterative hash algorithms. Key words: SHA-256 (384,512), Iteration Bound Analysis, Throughput Optimum Architecture
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
Added 09 Jun 2010
Updated 09 Jun 2010
Type Conference
Year 2007
Where WISA
Authors Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
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