An iterative improvement algorithm for low power data path synthesis

We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects of several behavioral synthesis tasks like module selection, clock selection, scheduling, and resource sharing on supply voltage and switched capacitance need to be considered simultaneously to fully derive the benefits of design space exploration at the behavior level. Recentwork hasestablishedthe importanceof behavioralsynthesisin low powerVLSI design. However,most of the algorithms that have been proposedseparate these tasks and perform them sequentially, and are hence not able to explore the tradeoffs possible due to their interaction. We present an efficient algorithm for performing scheduling, clock selection, module selection, and resource allocation and assignment simultaneously with an aim of reducing the power consumption in the synthesized data path. The algorithm, which is based on an iterative ...

• Type: Conference
• Year: 1995
• Where: ICCAD
• Authors: Anand Raghunathan, Niraj K. Jha
• Keywords: Behavioral Synthesis, Clock Selection, Hardware, ICCAD 1995, Supply Voltages