The KIT COSMOS Processor: Introducing CONDOR

Abstract In this paper, we propose a microprocessor architecture which eciently utilizes nextgeneration semiconductor technology. While the technology makes it possible to integrate a lot of functional units on a single chip, contemporary microprocessors can not exploit much instruction level parallelism so that the units are wasted. Our proposal based on Simultaneous Multi-Threading (SMT) increases the number of benecial instructions and thus the functional units work eciently. As well as application programs, a binary code translator which dynamically optimizes the applications on-the- y is executed on the SMT. We call this mechanism CONcurrent Dynamic OptimizeR (CONDOR). Based on the CONDOR architecture, performance of the applications are improved as well. We are currently studying the KIT COSMOS processor which utilizes CONDOR. This paper describes some ideas behind the architecture and the goal of this study.

• Type: Conference
• Year: 2000
• Where: PDPTA
• Authors: Toshinori Sato, Itsujiro Arita
• Keywords: Bene Cial Instructions, Functional Units, Instruction Level Parallelism, PDPTA 2000, PDPTA 2007