Latency-Driven Design of Multi-Purpose Systems-On-Chip

Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 [e-mail] Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 [e-mail] Deep submicron technology has two major ramifications on the design process: (i) critical paths are being dominated by global interconnect rather than gate delays and (ii) ultra high levels of integration mandate designs that encompass numerous intrasynchronous blocks with decreased functional granularity and increased communication demands. These factors emphasize the importance of the on-chip bus network as the crucial highperformance enabler for future systems-on-chip. By using independent functional blocks with programmable connectivity, designers are able to build systems-on-chip capable of supporting different applications with exceptional levels of resource sharing. To address challenges in this design paradigm, we have developed a methodology that enables efficient bus network desig...

• Type: Conference
• Year: 2001
• Where: DAC
• Authors: Seapahn Meguerdichian, Milenko Drinic, Darko Kirovski
• Keywords: Bus Network Design, DAC 2001, Design Automation, Multi-purpose Systems-on-chip, On-chip Bus Network