Sciweavers

Share
DATE
2010
IEEE

Layout-aware pseudo-functional testing for critical paths considering power supply noise effects

9 years 5 months ago
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of the circuits. In this paper, we propose novel layout-aware pseudofunctional testing techniques to tackle the above problem. Firstly, by taking the circuit layout information into account, functional constraints related to delay faults on critical paths are extracted. Then, we generate functionally-reachable test cubes for every true critical path in the circuit. Finally, we fill the don’t-care bits in the test cubes to maximize power supply noises on critical paths under the consideration of functional constraints. The effectiveness of the proposed methodology is verified with large ISCAS’89 benchmark circuits.
Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu
Added 10 Jul 2010
Updated 10 Jul 2010
Type Conference
Year 2010
Where DATE
Authors Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu
Comments (0)
books