Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction

To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in the Vdd-programmable method consume a large amount of leakage. In this paper, we develop chip-level dualVdd assignment algorithms to guarantee that no low-Vdd interconnect switch drives high-Vdd interconnect switches. This removes the need of Vdd-level converters and reduces

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Yan Lin, Lei He
• Keywords: DAC 2005, Design Automation, Low-Vdd Interconnect Switch, Unused Interconnects