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2005
ACM

Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction

10 years 2 months ago
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in the Vdd-programmable method consume a large amount of leakage. In this paper, we develop chip-level dualVdd assignment algorithms to guarantee that no low-Vdd interconnect switch drives high-Vdd interconnect switches. This removes the need of Vdd-level converters and reduces
Yan Lin, Lei He
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2005
Where DAC
Authors Yan Lin, Lei He
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