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2008
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Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction

8 years 4 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinational blocks to be used by slower blocks to meet a more stringent clock cycle time. Instead, we can leverage on the borrowed time to achieve leakage power reduction during gate sizing and/or dual Vth assignment. In this paper, we present the first approach to the best of our knowledge for integrating clock skew scheduling, threshold voltage assignment, and gate sizing into one optimization formulation. Over 29 circuits in the ISCAS89 benchmark suite, this integrated approach can reduce leakage power by as much as 55.83% and by 18.79% on average, compared to using combinational circuit based power optimization on each combinational block without considering clock skews. Using a 65nm dual Vth technology library, this corresponds to a 23.87% peak reduction (6.15% on average) in total power at the ambient operating t...
Min Ni, Seda Ogrenci Memik
Added 19 Oct 2010
Updated 19 Oct 2010
Type Conference
Year 2008
Where DAC
Authors Min Ni, Seda Ogrenci Memik
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