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MICRO
2007
IEEE

Leveraging 3D Technology for Improved Reliability

9 years 7 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower supply voltages have increased the vulnerability of computer systems towards transient faults. An increase in within-die and die-to-die parameter variations has also led to a greater number of dynamic timing errors. A potential solution to mitigate the impact of such errors is redundancy via an in-order checker processor. Emerging 3D chip technology promises increased processor performance as well as reduced power consumption because of shorter on-chip wires. In this paper, we leverage the “snap-on” functionality provided by 3D integration and propose implementing the redundant checker processor on a second die. This allows manufacturers to easily create a family of “reliable processors” without significantly impacting the cost or performance for customers that care less about reliability. We comprehens...
Niti Madan, Rajeev Balasubramonian
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where MICRO
Authors Niti Madan, Rajeev Balasubramonian
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