Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems

13 years 10 months ago

Download www.csl.cornell.edu

Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches, adding a voltage scaling design providing ﬁner control of power budgets. This delivers good performance and low power, consuming 34% of the power of previous designs.

Major Bhadauria, Sally A. McKee, Karan Singh, Gary

Real-time Traffic

HIPEAC 2007 | Reduces Dynamic Power | Reduces Leakage Power | System Software | Voltage Scaling |

claim paper

» Software data spreading leveraging distributed caches to improve single thread performance

» Compilermanaged partitioned data caches for low power

» Eliminating interprocess cache interference through cache reconfigurability for realtime a...

» Code compression for low power embedded system design

» Leveraging onchip networks for data cache migration in chip multiprocessors

» A low power frontend for embedded processors using a blockaware instruction set

» Dynamic Voltage and Cache Reconfiguration for Low Power

» Procedure Based Program Compression

Post Info
More Details (n/a)

Added	07 Jun 2010
Updated	07 Jun 2010
Type	Conference
Year	2007
Where	HIPEAC
Authors	Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson

Comments (0)

Sciweavers

Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems

HIPEAC 2007 | Reduces Dynamic Power | Reduces Leakage Power | System Software | Voltage Scaling |

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers