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2002
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LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

9 years 7 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods are based on either (i) inserting dedicated interconnect selftest structures (leading to significant area overhead), or (ii) using existing logic BIST structures (e.g., LFSRs), which often result in poor defect coverage. Additionally, it has been shown that power consumed during testing can potentially become a significant concern. In this paper, we present Logic-Interconnect BIST (LIBIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing LFSR structures but generates high-quality tests for interconnect crosstalk, while minimizing area overhead and interconnect power consumption. On applying LI-BIST to a DSP chip, we achieved crossta...
Krishna Sekar, Sujit Dey
Added 16 Jul 2010
Updated 16 Jul 2010
Type Conference
Year 2002
Where VTS
Authors Krishna Sekar, Sujit Dey
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