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2007
ACM

Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms

9 years 2 months ago
Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is barrier instructions which are used to perform global synchronization across parallel processors. This scenario calls for a lightweight synchronization infrastructure. In this work we describe a lightweight barrier support library for a non-cache-coherent MPSoC architecture. The library is coupled with a parallelizing compiler front-end to set up a complete automated flow which, starting from a sequential code, produces the parallelized binary code that can be directly executed onto an MPSoC target (a multicore non-cache-coherent ARM7 platform). This tool-flow has been characterized in terms of system performance and energy. Categories and Subject Descriptors D.3.4 [Software]: Programming Languages--Run-time Environments General Terms Performance Keywords Barrier synchronization, code parallelization, MPSoCs...
Andrea Marongiu, Luca Benini, Mahmut T. Kandemir
Added 12 Aug 2010
Updated 12 Aug 2010
Type Conference
Year 2007
Where CASES
Authors Andrea Marongiu, Luca Benini, Mahmut T. Kandemir
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