On-Line Histogram Equalization for Flash ADC

— We present theory, design and measurement results for an on-line histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.35µm CMOS. The user simply turns on ”training mode” for a few seconds, while the algorithm automatically adjusts comparator levels to match the observed input signal distribution. This results in signal conversion with equal probability for each of the output codewords. The new architecture is an extension of a flash ADC incorporating an adaptive floating gate comparator and control circuits for automatic programming of the reference levels. Experiments show output codes with at least 5.9 bits entropy for ramp, sine and Gaussian random signals after adaptation. Uniform programming produces 5.7 ENOB for input frequencies up to 200MHz and maximum DNL and INL of 0.24 LSB and 0.79 LSB at Nyquist rate, while equalization produces 5.3 ENOB up to 600MHz.

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire
• Keywords: Comparator Levels, Histogram Equalization Algorithm, Input Signal Distribution, ISCAS 2007