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2006
IEEE

Off-Line Testing of Delay Faults in NoC Interconnects

9 years 5 months ago
Off-Line Testing of Delay Faults in NoC Interconnects
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for atspeed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for online testing.
Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimu
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where DSD
Authors Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng
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