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LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory

9 years 1 months ago
LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory
Phase change memory (PCM) has emerged as a promising technology for main memory due to many advan­ tages, such as better scalability, non-volatility and fast read access. However, PCM's limited write endurance restricts its immediate use as a replacement for DRAM. Recent studies have revealed that a PCM chip which integrates millions to billions of bit cells has non-negligible variations in write endurance. Wear leveling techniques have been proposed to balance write operations to different PCM regions. To further prolong the lifetime of a PCM device after the failure of weak cell, techniques have been proposed to remap failed lines to spares and to salvage a PCM device that has a large number of failed lines or pages with graceful degradation. However, current wear-leveling and salvaging schemes have not been designed and integrated to work cooperatively to achieve the best PCM device lifetime. In particular, a non­ contiguous PCM space generated from salvaging complicates wear...
Lei Jiang, Yu Du, Youtao Zhang, Bruce R. Childers,
Added 19 Dec 2011
Updated 19 Dec 2011
Type Journal
Year 2011
Where DSN
Authors Lei Jiang, Yu Du, Youtao Zhang, Bruce R. Childers, Jun Yang 0002
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