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2010

LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization

8 years 5 months ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. LOPASS includes three major components: 1) a flexible high-level power estimator for FPGAs considering the power consumption of various FPGA logic components and interconnects; 2) a simulated-annealing optimization engine that carries out resource selection and allocation, scheduling, functional unit binding, register binding, and interconnection estimation simultaneously to reduce power effectively; and 3) a -cofamily-based register binding algorithm and an efficient port assignment algorithm that reduce interconnections in the data path through multiplexer optimization. The experimental results show that LOPASS produces promising results on latency optimization compared to an academic high-level synthesis tool SPARK. Compared to an early commercial high-level synthesis tool, namely, Synopsys
Deming Chen, Jason Cong, Yiping Fan, Lu Wan
Added 22 May 2011
Updated 22 May 2011
Type Journal
Year 2010
Where TVLSI
Authors Deming Chen, Jason Cong, Yiping Fan, Lu Wan
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