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2005
IEEE

A Low Area and Low Power Programmable Baseband Processor Architecture

9 years 4 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a configurable network. Design choices are motivated by the inherent properties of the baseband algorithms used in different types of radio systems. A large degree of hardware reuse between algorithms and standards, careful selection of accelerators, and low memory cost allows very area and power efficient implementation of multistandard radio baseband processors. A demonstrator chip for 802.11a/b/g physical layer baseband processing was manufactured in 0.18 µm CMOS. The silicon area is 2.9 mm2 , including all memories.
Eric Tell, Anders Nilsson, Dake Liu
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where IWSOC
Authors Eric Tell, Anders Nilsson, Dake Liu
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