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ASPDAC
2006
ACM

Low area pipelined circuits by multi-clock cycle paths and clock scheduling

13 years 9 months ago
Low area pipelined circuits by multi-clock cycle paths and clock scheduling
— A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algorithm analyzes the pipelined circuit and determines the intermediate registers that can be removed. An efficient subsidiary algorithm is presented that computes the minimum feasible clock period of a circuit containing multi-clock cycle paths. Experiments with a pipelined adder and multiplier verify that the proposed algorithm can reduce the number of intermediate registers without degrading performance, even when delay variations exist.
Bakhtiar Affendi Rosdi, Atsushi Takahashi
Added 13 Jun 2010
Updated 13 Jun 2010
Type Conference
Year 2006
Where ASPDAC
Authors Bakhtiar Affendi Rosdi, Atsushi Takahashi
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