Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor

This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordlengths avoiding time and power consuming reconfiguration. The new data-path can operate in SIMD fashion and guarantees high parallelism levels when operations on lower precisions are executed. It also supports IEEE-754 compliant single precision floatingpoint addition and multiplication. The proposed circuit has been characterized using VIRTEXII XILINX devices, but it can be efficiently used also in other FPGA families.

• Type: Conference
• Year: 2005
• Where: FPL
• Authors: Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello
• Keywords: FPGA-based Multimedia Processors, FPL 2005, Power Consuming Reconfiguration, Wordlengths Avoiding Time