A Low Energy Set-Associative I-Cache with Extended BTB

This paper proposes a low-energy instruction-cache architecture, called history-based tag-comparison (HBTC) cache. The HBTC cache attempts to re-use tag-comparison results for avoiding unnecessary way activation in setassociative caches. The cache records tag-comparison results in an extended BTB, and re-uses them for directly selecting only the hit-way which includes the target instruction. In our simulation, it is observed that the HBTC cache can achieve 62% of energy reduction, with less than 1% performance degradation, compared with a conventional cache.

• Type: Conference
• Year: 2002
• Where: ICCD
• Authors: Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
• Keywords: Cache Records, Conventional Cache, Hardware, HBTC Cache, ICCD 2002