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DAC
2005
ACM

A low latency router supporting adaptivity for on-chip interconnects

10 years 2 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip (NoC) have been proposed. The NoC routing algorithm significantly influences the performance and energy consumption of the chip. We propose a router architecture which utilizes adaptive routing while maintaining low latency. The two-stage pipelined architecture uses look ahead routing, speculative allocation, and optimal output path selection concurrently. The routing algorithm benefits from congestionaware flow control, making better routing decisions. We simulate and evaluate the proposed architecture in terms of network latency and energy consumption. Our results indicate that the architecture is effective in balancing the performance and energy of NoC designs. Categories and Subject Descriptors: [B.4 I/O and Data Communications]:Interconnections(Subsystems), [B.8:Performance and Reliability]:Performance ...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2005
Where DAC
Authors Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das
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