Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems

The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this paper, we propose two techniques, namely Soft Error Mitigation (SEM) and Soft and Timing Error Mitigation (STEM), for protecting combinational logic blocks from soft errors. Our first technique (SEM), based on distributed and temporal voting of three registers, unloads the soft error detection overhead from the critical path of the systems. Our second technique (STEM) adds timing error detection capability to guarantee reliable execution in aggressively clocked designs that enhance system performance by operating beyond worst-case clock frequency. We also present a specialized low overhead clock generation scheme that ably supports our proposed techniques. Timing annotated gate level simulations, using 45nm libraries, of a pipelined adder-multiplier and DLX processor show that both our techniques achieve near 1...

• Type: Conference
• Year: 2009
• Where: DSN
• Authors: Naga Durga Prasad Avirneni, Viswanathan Subramanian, Arun K. Somani
• Keywords: Computer Networks, DSN 2009, Soft Error, Soft Error Mitigation, Timing Error