A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards

Abstract— In this paper we present an efficient system-onchip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards. The decoder has a scalable datapath and can be dynamically reconfigured to support multiple 4G standards. We utilize a pipelined version of the layered belief propagation algorithm to achieve partial-parallel decoding of structured LDPC codes. Instead of using the sub-optimal Minsum algorithm, we propose to use the powerful belief propagation (BP) decoding algorithm by designing an area-efficient softinput soft-output (SISO) decoder. Two power saving schemes are employed to reduce the power consumption up to 65%. The decoder has been synthesized, placed, and routed on a TSMC

• Type: Conference
• Year: 2008
• Where: SOCC
• Authors: Yang Sun, Joseph R. Cavallaro
• Keywords: 1-gbps Ldpc Decoder, Belief Propagation, Decoder, Education, SOCC 2008