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VLSID
1997
IEEE

Low-Power Configurable Processor Array for DLMS Adaptive Filtering

13 years 7 months ago
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoffbetween algorithmic performance and power dissipation. This architecture is then extended to derive a configurable processor array (CPA), which is configurable for filter order, sample period and power reduction factor. The hardware overhead incurred for configurability is minimal.
S. Ramanathan, V. Visvanathan
Added 06 Aug 2010
Updated 06 Aug 2010
Type Conference
Year 1997
Where VLSID
Authors S. Ramanathan, V. Visvanathan
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