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2005
ACM

A low-power crossroad switch architecture and its core placement for network-on-chip

11 years 11 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should possibly match communication workflows among these components. In this paper, we first propose an interconnection architecture for SoC, which uses crossroad switches to construct a dedicated communication path dynamically between any two cores. We then present a design methodology for constructing network on chip (NoC) for application-specific computer systems with profiled communication characteristics. We design a core placement tool, which automatically maps cores to a communication topology such that we can minimize the total communication energy. Experimental results show that the design methodology can generate optimized on-chip networks with fewer resources than ...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where ISLPED
Authors Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
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