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ASPDAC
2005
ACM

Low-power domino circuits using NMOS pull-up on off-critical paths

9 years 11 months ago
Low-power domino circuits using NMOS pull-up on off-critical paths
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose a scheme to reduce the power consumption of combinational domino logic blocks while maintaining the performance. We replace the PMOS precharge transistor with an NMOS transistor to reduce the overall power consumption of the gate at the expense of higher delay. We use a heuristic algorithm to replace the fast, high power gates on the off-critical paths with slower, low power gates while maintaining the circuit performance. Our technique reduces dynamic energy of ISCAS’85 circuits by 16.25%.
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where ASPDAC
Authors Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
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